48 lines
2.5 KiB
Markdown
48 lines
2.5 KiB
Markdown
# TextureTaffy
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A utility to create compressed textures, in BC1 (DXT1), BC3 (DXT5), BC4, BC5, BC6(U)H and BC7 compression formats, with the [KTX File Format Version 2.0](https://registry.khronos.org/KTX/specs/2.0/ktxspec.v2.html) (KTX2) file format.
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Multithreaded, uses ispc_texcomp for compression, and stb_image for image loading.
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![Screenshot](screenshot.webp)
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## Requirements
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* C++ compiler supporting at least c++17. Tested on GCC, clang and MSVC 2022.
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* [The Meson build system](https://mesonbuild.com/)
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* [Intel® Implicit SPMD Program Compiler](https://ispc.github.io/)
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## Building
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```
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meson setup build [--buildtype=release] -Dcpp_std=c++17
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meson compile -C build
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```
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## Usage
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```
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Usage: TextureTaffy [cube|array] <input> [input2, input3...] <output> <format> [fast|normal|slow|veryslow]
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Formats:
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BC1 - (DXT1) 5:6:5 Color, 1 bit alpha. 8 bytes per block.
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BC1_SRGB - (DXT1) 5:6:5 Color, 1 bit alpha. 8 bytes per block.
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BC4 - Greyscale, 8 bytes per block.
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BC5 - 2x BC4 images. 16 bytes per block.
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BC3 - (DXT5) BC1 Color, BC4 Alpha, 16 bytes per block.
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BC3_SRGB - (DXT5) BC1 Color, BC4 Alpha, 16 bytes per block.
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BC6H - 16 bit RGB, no alpha. Signed. 16 bytes per block.
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BC7 - 8 bit RGBA - Good general purpose. 16 bytes per block.
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BC7_SRGB - 8 bit RGBA - Good general purpose. 16 bytes per block.
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```
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## Notes and limitations
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* Uses stb_image for image loading. Therefore only supports radiance HDR images, not OpenEXR.
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* KTX2 writer probably isn't the most robust, but it works for what I need in my pipeline.
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* ispc_texcomp doesn't appear to have seperate options for encoding linear BC1, BC3 and BC7 textures. The only difference is the method I use for scaling and the format header.
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Therefore the linear textures I output are probably very non-optimal. BC4/BC5/BC6 is probably best for linear data.
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* Tested with LDR and HDR single images and cubemaps. May work with 3D textures and arrays, but not tested.
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* Only supports BC1, BC3, BC4, BC5, BC6H and BC7 compression formats, ETC and ASTC are implemented by ispc_texcomp,
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but I haven't had a need for them yet. Pull requests welcome!
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* Based on my testing, the SSE4 code path is faster than AVX2 on modern AMD processors, but AVX2 is faster on intel.
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from what I've read, AMD implements AVX2 in slow microcode. ISPC doesn't allow easily selecting the instruction set at runtime,
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so I've added a little hack to detect AMD and use SSE4 in that case.
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* Only supports x86/x64 processors. In theory ispc_texcomp has support for ARM NEON extensions for example, but I haven't had time to look at that.
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